Measurement
The connectivity tax is our chip’s design brief.
We ran the same surface code on degree-3 hardware and in degree-4 simulation — the gap between them is why our lattice looks the way it does.
Key takeaways
- Routed onto degree-3 heavy-hex hardware, the distance-5 surface-code circuit costs 2,095 (Z) / 2,158 (X) two-qubit gates against 400 in the abstract circuit — a 5.2–5.4× inflation, read per basis from the run manifest.
- The routed distance-5 syndrome round stretches to 16.98 µs, and data qubits idling through it accumulate 11.54% error per round — before any gate error is counted.
- At distance 5 the measured logical state is statistically indistinguishable from chance in both bases: the observed distribution leaves nothing for any decoder to recover.
- In circuit-level simulation on a degree-4 lattice with routing margin, the same code and decoder suppress error with distance (Λ fits: 1.97 Z / 1.85 X at p = 0.005) and the circuit routes with zero added SWAPs.
Why measure before designing?
Most quantum hardware programmes draw the chip first and discover its costs later. We inverted the order: before committing to a lattice, we spent months running encoded-qubit experiments on commercial superconducting processors, as paying customers, to find exactly where a surface code loses its logical state on hardware that exists today.
What did the hardware say?
The rotated surface code assumes each data qubit talks to four neighbours. Heavy-hex hardware provides three. The compiler bridges the difference with routing — SWAP operations decomposed into native two-qubit gates — and each added gate pays the device’s error rate. The run manifest puts the cost at distance 3 at 279 (Z) / 264 (X) routed two-qubit gates against 72 abstract; at distance 5, 2,095 (Z) / 2,158 (X) against 400. Re-transpiling the archived circuits recovers the configuration to within 5%, so the counts are reproducible, not folklore. Basis-averaged and rounded, they are the 270 and 2,100 quoted on our summary surfaces.
Gates are only half the bill. Routing stretches the distance-5 syndrome round to 16.98 µs, and a data qubit idling through that window accumulates 11.54% error per round at the device’s measured coherence. Adding that measured idle channel to the gate-count model closes 89% of the gap to the hardware result. At distance 3 the Z-basis logical error came out at 0.152 per cycle, with the X basis marginal at 0.305; at distance 5 the decoded state came out at chance in both bases — the observed distribution leaves nothing for any decoder to recover.
What did the simulation say?
The same code, the same decoder, an ideal degree-4 lattice: across 14.4 million shots of circuit-level simulation, logical error falls with every added code distance in both bases — exponential fits give Λ = 1.97 (Z) and 1.85 (X) at p = 0.005 — and with routing margin on the lattice the circuit transpiles with zero added SWAPs, landing exactly on the abstract gate count. The failure and the fix are the same experiment, run on two geometries. The same simulation independently reproduces the published circuit-level surface-code threshold — the instrument is checked against the literature before it is pointed at our own result.
What design brief fell out?
That is the entire architectural argument for Nandi Q1: a degree-4 lattice with room to route. It was not chosen from a roadmap or borrowed from a datasheet — it was derived from a failure we measured and a fix we simulated, and every number in the argument carries a job ID.
Conditions. Hardware figures: rotated surface code on a 156-qubit Heron-class processor, decoded offline with minimum-weight matching; gate counts per basis from the archived run manifest. Simulation: Stim + PyMatching, circuit-level depolarizing noise, ideal degree-4 lattice, 300,000 shots per point. Simulation and hardware never share an axis. Conditions and job IDs: the ledger.