Approach
Measure first. Then design.
A quantum hardware team that tells you exactly what it has and hasn’t done. We say which rung of the ladder we are on — designed, simulated, fabricated, or measured. We are on the first two.
Most hardware programs draw the chip first and discover its costs later. We inverted that. Before drawing a single mask, our founding team spent months measuring — on rented, commodity superconducting processors — exactly where today’s devices lose their qubits. The result is a design brief written by experiments instead of ambition: every number is on the ledger, with its caveats attached.
Thesis — measurement
Measure first
We characterize before we design. The founding measurement: on degree-3 connectivity, the surface code decoheres with growing distance; on a degree-4 lattice in simulation, the same code and decoder suppress errors. The gap is the cost of the missing degree — measured, not argued.
Thesis — architecture
Design for the code
Error correction is the customer of the chip. Connectivity and layout are chosen so the cheapest correcting block is cheap on our lattice — a statement about geometry, not about any vendor’s device quality. Our hardware-aware layout work shows how much routing alone can waste.
Thesis — place
Build in India
Bootstrapped, design-stage, and here on purpose. India’s National Quantum Mission has set the stage; we want to be one of the teams that delivers on it. No affiliation implied — when something is signed, we’ll announce it with the name of the thing on it.
Now
What we are building.
Our first chip is a four-qubit superconducting design in progress — not yet silicon. The design package — schematics, simulation, layout — is the milestone we report on 30 August, and the report will say what closed and what did not.
On coherence: we have design targets and we’ll publish them labelled as targets. We do not have measured numbers and won’t until something is fabricated and put in a fridge. Anyone quoting you a coherence number off a layout is quoting you an aspiration.
Direction, not dates
Four qubits to eight, then sixteen — and, over time, toward manufacturing at scale. Each generation is gated on what the previous one measured, so no date is attached to a qubit count.
Discipline
How we validate before we spend a shot.
Every hardware run goes through a simulation pipeline with a three-rung abort ladder: the noiseless model must be error-free, the noisy model must track an independent simulator, and the larger code must beat the smaller one per cycle — a hard assertion — before a single shot is purchased. The same pipeline, run at scale in simulation on an ideal degree-4 lattice, independently reproduces the published circuit-level surface-code threshold — which is why the hardware measurements from the same pipeline can be trusted. That large sweep is simulation, not hardware, and is never presented otherwise.
Before committing a run we compute a screening rule: expected two-qubit faults per round — the routed gate count times the device’s error rate. Above roughly one, no decoder can help, so the run is not made. An engineering rule validated out-of-sample against measurements on rented hardware and in simulation; it predicts when a run cannot work, not how well a run will work.
Every future chip generation has a locked, dated prediction and pass/fail criterion registered before the chip exists. The first experiment our first chip will run was pre-registered on 2026-07-30 — the simulation caught a real physics bug before it could reach hardware. When the chip is measured we run the identical protocol and report deviations, not hide them. Nothing is claimed above its achieved rung.
The control stack
Our founding team has written and synthesis-verified the classical control plane a quantum chip needs — pulse sequencing, detector capture, servo loops, timing, entropy — plus a hand-written RV32I control core and exhaustively test-benched small-code bit-flip correction datapaths. Simulation-verified; no board flashed, no timing closure, no silicon. “Compiles and synthesizes clean” is not “works on hardware”, and no latency figure is claimed.
Publishing
How we publish.
- Every claim carries the thing that backs it. Reserved words — measured, demonstrated, verified — are used only with hand-over-the-data results.
- Negatives are published in full — a page that hides its unfavourable data is not credible.
- Retractions are dated and stay visible — same channel, same day, never a silent delete.
- Simulated and measured never share an axis. Every figure wears its rung: designed, simulated, fabricated, or measured.
- The test we run on our own claims: any metric that ranks a repetition code above a surface code is broken. If our numbers look good under a broken metric, they are not good.
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