Approach — how we design quantum processors

Before designing our first processor, we studied where existing quantum hardware loses performance and used those findings to define the architectural requirements for our system.

Measure first.

We characterize before we design. Our experiments examine how connectivity, routing, gate overhead and error-correction requirements affect logical performance on superconducting quantum hardware.

Every reported result is labelled by its stage: designed, simulated, fabricated, or measured.

Design for the code.

Error correction is a primary architectural requirement. Our processor is being designed around the connectivity and routing requirements of quantum error correction, with the goal of reducing unnecessary operations and preserving the time available for computation. The architecture is designed to make error correction practical at the hardware level.

From experiment to architecture.

Measurements on existing hardware identified connectivity and routing as important limitations for larger error-correction circuits. Those observations informed the architecture of our first processor. Degree-4 connectivity is a core design requirement.

The implementation details of our processor architecture remain proprietary. The measurements themselves are on the ledger, with research papers in preparation.

Validate before hardware.

We use simulation to test architectures, circuits and error-correction strategies before committing experiments to quantum hardware — evaluating circuit behaviour, expected logical performance, routing overhead, error sensitivity and architecture-level trade-offs. Hardware experiments then test whether those predictions survive real device noise.

Simulated results are never presented as hardware measurements. Every figure below is tagged with what it is.

Figure 1. Simulated per-cycle logical error vs code distance at p = 0.005, both bases. Each added distance step cuts the error by Λ = 1.97 (Z) / 1.85 (X). 300,000 shots per point.

Figure 2. Simulated per-cycle logical error vs physical error rate, Z basis, distances 3–9. Below the ~1% threshold, larger codes win — at p = 0.002, distance 9 sits over 100× below distance 3. 300,000 shots per point.

Figure 3. Routed two-qubit gates per syndrome-cycle circuit. Degree-3 values are per-basis from the hardware run manifest; the degree-4 value is a transpiled schedule with routing margin — zero added SWAPs.

Figure 4. The idle budget: error per data qubit per syndrome round, from a model calibrated to the device’s measured T1/T2. Markers: the distance-3 round at 8.08 µs → 5.75%, and the distance-5 round at 16.98 µs → 11.54% per data qubit per round.

Simulation: Stim + minimum-weight matching, circuit-level noise, 300,000 shots per point, per-cycle rates, both bases. Gate counts: archived hardware run manifest. Full conditions and job IDs: the ledger.

Future chip generations will be tested against predefined experimental criteria rather than retrospective benchmarks.

Hardware and control.

Quantum processors require tightly integrated quantum and classical control. We are developing the control architecture alongside the processor, so that measurement, decision-making and feedback are part of the system rather than an external layer. Implementation details remain proprietary until they are ready for disclosure.

Our publishing standard.

We publish experimentally supported results and the scientific conclusions that follow from them. Measured results are distinguished from simulations. Every claim travels with the conditions that make it true, and the data to check it.

The principle is simple: measure first, design second, and let the data decide what comes next.