Building India's quantum chip.
We design superconducting quantum processors in India — and publish exactly what we measure.
30 Aug 2026 A status report on our first chip design — what closed, and what is still open. see the blog
Why we exist
Design and build India's quantum chip — and publish exactly what we measure.
Processors designed around the error correction they run. We measured what connectivity costs an error-correcting code on rented hardware — that measurement is the design brief for our first device.
Early results — founding team
Measurement notes
¹ [[4,2,2]] detection code, three-basis, post-selected; rented IBM hardware, 2026-08. d9npkuuij12s73fu66qg ↩
² 31 independent pairs, witness-certified 31/31; post-selected, rented hardware, 2026-08. d9mf6308csec73fa3o7g ↩
³ One-basis repetition ladder, 22 → 4 failures per 100k shots; rented hardware, 2026-08. d9nppncsfqic73arb48g ↩
⁴ Compiler metrics: 3,710 → 615 two-qubit gates, zero added SWAPs; our own before/after, 2026-08. ↩
Full caveat blocks, dates, and write-ups: the results ledger.
The device
Designed around the code it runs.
The measurements above choose the geometry: a degree-4 lattice, so the correcting code routes without detours.
How we operate
Measured on rented hardware, at commodity cost, by a small team — pre-registered, with the raw shots archived and every number re-derived offline.
Our first chip is in design.
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